1. Field of the Invention
The present invention relates to a semiconductor device, more particularly, to a semiconductor device having bump(s) (projecting electrode(s) for connection) for electrical and mechanical connection to a wiring pattern of a circuit board when mounted on the circuit board and a method of fabricating the same.
2. Description of the Related Art
Semiconductor devices of the surface-mounting type are increasingly used as a semiconductor device constituting an integrated circuit (IC) or a large scale integrated (LSI) circuit.
Some semiconductor devices of surface-mounting type have multiple bumps provided on the surfaces thereof for electrical and mechanical connection to a wiring pattern of a circuit board when mounted on the circuit board. As an example, the configuration of a bump in a straight wall shape is shown in FIG. 20.
FIG. 20 is a sectional view showing a portion of a conventional semiconductor device. On a semiconductor substrate 12 having an integrated circuit formed therein, multiple electrode pads 14 (only one is shown in FIG. 20) are provided for connection to an external circuit. An insulating film 16 having opening portions 16a each formed to cover the edge of each electrode pad 14 and to expose the inside portion thereof is provided on the entire surface of the semiconductor substrate 12. A lower electrode 19 is provided to be closely contacted with the periphery of the opening portion 16a of the insulating film 16 and the exposed portion of the electrode pad 14.
Additionally, provided on the lower electrode 19, there is a bump 36 formed in a straight wall shape.
In this semiconductor device, the bump electrode 36 is formed in a straight wall shape. In contrast, some semiconductor devices have bumps each formed in a mushroom shape in which the upper portion is larger than the base portion. However, a straight wall shape bump can have a less extended area in the lateral direction along the semiconductor substrate 12 to allow more bumps to be arranged at an increased density, thereby obtaining a finer pitch for connection to an external circuit.
Next, as an example of mounting a semiconductor device having the bump 36 formed as described above onto a circuit board, a structure for mounting on a glass substrate of a liquid crystal display panel is shown in FIG. 21.
The liquid crystal display panel is designated with reference numeral 40, in which a liquid crystal 43 is filled in between two glass substrates 41, 42 by a sealing material 44, and an area 8 corresponding to an extended portion of the lower glass substrate 42 with regard to the upper glass substrate 41 is an area for mounting a semiconductor device 10 which drives the liquid crystal display panel 40.
On the upper surface of the glass substrate 42, multiple wiring patterns 45 extending from the inside where the liquid crystal is filled toward the area 8 and multiple wiring patterns 46 serving as a connection terminal to the outside are formed.
To mount the semiconductor device 10 on the liquid crystal display panel 40, first, an anisotropic conductive adhesive 50 obtained by mixing conductive particles 52 into an insulating adhesive is applied on the area 8 of the glass substrate 42. Next, the semiconductor device 10 is disposed above the area 8 of the glass substrate 42 in alignment with the wiring patterns 45, 46 for connection to each bump 36, in an orientation upside down with respect to that of the semiconductor device 10 shown in FIG. 20.
In this way, with the semiconductor device 10 set on the substrate 42 applied with the anisotropic conductive adhesive 50, the semiconductor device 10 is pressed on the glass substrate 42 and is subjected to an annealing treatment so that each bump 36 is electrically connected to the wiring patterns 45, 46 through the conductive particles 52 in the anisotropic conductive adhesive 50. Simultaneously, the semiconductor device 10 is attached and fixed to the glass substrate 42 with the insulating adhesive in the anisotropic conductive adhesive 50.
Also, a flexible printed circuit (FPC) board 60 is disposed at its end portion above the portion of the glass substrate 42 that is formed with the wiring pattern 46. This FPC 60 is formed with a wiring pattern made of copper foil for providing an input signal to the semiconductor device 10.
This wiring pattern is also electrically connected to the wiring pattern 46 on the glass substrate 42 through the conductive particles 52 in the anisotropic conductive adhesive 50 and the end portion of the FPC is attached and fixed to the glass substrate 42.
Such a configuration ensures connections by the conductive particles 52 in the anisotropic conductive adhesive 50 between the bump 36 and the wiring pattern 45 on the glass substrate 42 as well as between the wiring pattern of the FPC 60 and the wiring pattern 46 on the glass substrate 42, respectively, thereby forming respective electrical connections. Mechanical connections are also formed by the insulating adhesive.
Thereafter, a mold resin 62 is applied on the upper surface of the connections for the semiconductor 10 and the FPC 60 and the surrounding regions thereof. This prevents moisture from entering the connections of the bump 36 and the wiring pattern 45 and the connections of the FPC 60 and the wiring pattern 46, and can provide mechanical protection to enhance reliability.
It is a matter of course that the semiconductor device having the bump as described above can be mounted not only on a liquid crystal display panel but also on various circuit boards in which a wiring pattern is formed on a resin substrate, ceramic substrate, and so on.
Next, the method of fabricating the conventional semiconductor device having a bump in a straight wall shape will be described using sectional views in FIG. 17 to FIG. 20.
First, as shown in FIG. 17, on the semiconductor substrate 12 having multiple electrodes pads 14 formed on the upper surface, the insulating film 16 is formed to cover the entire surface thereof. The opening portion 16a is formed by a photoetching technique on each electrode pad 14 such that the insulating film 16 is left only on the edge of each electrode pad 14 to expose the inside portion thereof.
Next, a common electrode film 32 is formed above the entire surface of the semiconductor substrate 12 having the electrode pad 14 and the insulating film 16 by a sputtering.
The common electrode film 32 is obtained by sequentially forming aluminum in the thickness of 0.8 .mu.m, chromium at 0.01 .mu.m, and copper at 0.8 .mu.m from the side of the semiconductor substrate 12 to make a three-layered structure. The common electrode film 32 serves both as a barrier layer for connecting to the electrode pad 14 and for preventing interdiffusion to the electrode pad 14, and as an electrode for forming the bump by an electroplating.
Thereafter, a photoresist (photoresistive resin) 18 shown in FIG. 18 is formed on the entire surface of the common electrode film 32 by a spin coating. An opening portion 18a is then formed in the portion in which the bump is to be formed by a photolithography technique.
As shown in FIG. 19, gold plating is plated onto the common electrode 32 in the opening portion 18a of the photoresist 18 to thereby form the bump 36 in a straight wall shape in a thickness ranging from 10 to 15 .mu.m.
After the photoresist 18 is removed, the bump 36 is used as a mask to etch the common electrode film 32 by a wet etching. Thus, as shown in FIG. 20, the common electrode film 32 is left only below the bump 36 to serve as the lower electrode 19.
After the above-mentioned steps, the semiconductor substrate 12 is cut into single pieces of a semiconductor chip in a dicing step to complete the semiconductor device.
However, the formation of the bump 36 through the above-mentioned steps has disadvantages in that the fabricating steps for the semiconductor device take a very long time and the steps require various apparatuses for forming films such as a sputtering apparatus, an etching apparatus, and an electroplating apparatus. Additionally, the above-mentioned steps have a disadvantage in that since the bump 36 must be formed in a thickness of 10 to 15 .mu.m by the electroplating method, the plating takes a relatively long time of approximately 30 to 40 minutes.
Furthermore, there exists a disadvantage in that the long time required for plating causes fine particles existing in the plating solution to easily attach to the portion in which the bump is to be formed and the particles serve as a nucleus to generate abnormal plating growth, thereby resulting in a reduction in the yield.
Since the fabrication of the conventional semiconductor device requires the plating step for a thick film for forming the bump 36 and the step for removal by etching the major part of the common electrode film 32 formed on the entire surface to form the lower electrode 19, it takes a long time until completion and the yield of the semiconductor device is easily reduced. Thus, it has been very difficult to reduce the fabrication cost.